Job Description
Join Nexus Future Labs at the forefront of technological revolution as we pioneer quantum computing solutions for 2026 and beyond. We seek a visionary Quantum Computing Architect to design next-gen systems that will redefine global industries. This role offers unparalleled opportunities to shape humanity's technological future while working with Nobel laureates and industry pioneers in our state-of-the-art San Francisco innovation hub.
Our team operates at the intersection of theoretical physics and practical application, developing quantum algorithms that solve previously unsolvable problems. You'll lead projects in quantum error correction, cryogenic engineering, and quantum machine learning, directly contributing to breakthroughs in pharmaceuticals, climate modeling, and artificial intelligence.
Responsibilities
- Design and implement scalable quantum computing architectures using superconducting and photonic systems
- Develop quantum error correction protocols to achieve fault-tolerant quantum computation
- Lead cross-functional teams in integrating quantum processors with classical computing frameworks
- Collaborate with research institutions to publish cutting-edge quantum algorithms in top-tier journals
- Optimize quantum circuits for real-world applications in cryptography and materials science
- Drive quantum security initiatives for next-generation blockchain systems
- Mentor junior engineers in quantum programming languages (Q#, Qiskit)
Qualifications
- PhD in Quantum Physics, Computer Science, or related field with 5+ years industry experience
- Expertise in quantum algorithms and quantum information theory
- Proficiency in quantum programming frameworks (Qiskit, Cirq, Q#)
- Published research in quantum error correction or fault tolerance
- Experience with cryogenic quantum systems and dilution refrigerators
- Demonstrated ability to lead complex technical projects with cross-disciplinary teams
- Deep understanding of quantum machine learning and quantum neural networks
- Strong background in high-performance computing architectures